1. Technical Field
The present invention relates to a test apparatus and an electronic device. More particularly, the present invention relates to a test apparatus for testing a device under test and an electronic device including therein a test circuit for testing a circuit under test.
2. Related Art
A test apparatus is known which tests a device under test (DUT) such as a semiconductor circuit. The test apparatus supplies a test signal having a predetermined logical pattern to the DUT, detects a signal output from the DUT in response to the supplied test signal, and compares the detected signal with an expected value, to judge whether the DUT is acceptable.
The test apparatus includes therein a pattern generator for sequentially generating a test pattern and a test signal output section for outputting a test signal having a logical pattern corresponding to the test pattern. The pattern generator sequentially reads an instruction from sequence data (a test instruction sequence) stored on a memory, and executes the read instruction. The pattern generator then reads from the memory pattern data corresponding to the executed instruction, and sequentially outputs the read pattern data as the test pattern. In this way, the test apparatus can supply the test signal having a predetermined logical pattern to the DUT.
The pattern generator can also execute sequence data described by using subroutines as disclosed in Unexamined Japanese Patent Application Publication No. 2001-194431, for example. When executing a subroutine call instruction described within a main test instruction sequence, the pattern generator reads a corresponding sub test instruction sequence from the memory and executes the read sub test instruction sequence. In this way, the pattern generator enables a test instruction sequence that is repeatedly executed to be stored as a single instruction sequence.
Here, the sequence data has therein timing set information described in correspondence with each instruction. The timing set information designates a timing of outputting a corresponding test pattern. Therefore, the pattern generator executes different instructions for generating test patterns which are the same but generated at different timings. In other words, the pattern generator can not store, as a single subroutine, test instruction sequences which generate the same test pattern but have different timings for the test pattern generation to be stored.